In memory qualification and validation, proper timing between a memory controller and DRAM chips must be ensured. The memory controller must ensure that chip select meets setup and hold time tolerances at the DRAM chip. Current methods to train chip select is achieved by the cumbersome method of extracting trace length and delays of chip select and clock signals for each and every board type using various printed circuit board trace length extraction tools. With the help of a software algorithm, the delays are analyzed and compensated for.
The current methodology is error prone as it involves interaction of various tools, software and manual interpretation of results. Further, it is time consuming as all the tools need to be set up and loaded with the proper constraints and the process must be repeated for every possible board type and every possible memory configuration. Finally, the methodology is not ideal because as the frequency of DRAM increases, the available chip select and clock eye width decreases making it increasingly difficult to obtain a common skew compensation across the entire silicon process range.